In a memory array such as a register file array, the minimum operating voltage (VCCmin) of the memory array is typically limited by the write and/or read operation of the memory array. This is due to the contention between the negative-channel metal-oxide-semiconductor field effect transistor (MOSFET) (NMOS) devices and the positive-channel MOSFET (PMOS) devices in the memory array. This may pose a problem for a system that employs the memory array if the VCCmin of the memory array limits the VCCmin of the entire system.
FIG. 1 illustrates a circuit 100 of a prior art register file bit cell 110. The prior art register file bit cell 110 has eight transistors (8T) and the cross-coupled transistors 111, 112, 113, and 114 store the bit value of the prior art register file bit cell 110. The transistors 115 and 116 are utilized for write operations of the prior art register file bit cell 110 and the transistors 117 and 118 are utilized for read operations of the prior art register file bit cell 110. The transistors 119, and 120 driven by the inverter 130 act as bit line keeper and prevent noise on the read bit line 170. One of ordinary skill in the relevant art will readily appreciate the workings of the read and write operations of the prior art register file bit cell 110 and therefore shall not be discussed herein.
Various techniques such as voltage collapsing of the operating voltage (VCC) for improvement of the VCCmin during a write operation of the memory array and using programmable or delayed keeper to improve the VCCmin during a read operation have been proposed.